This disclosure relates to the doping of a substrate via a dopant containing polymer film that is disposed upon the substrate.
One of the challenges of scaling electronic devices down to the nanometer regime (sizes less than 100 nanometers (nm)) is achieving controlled doping of semiconductor materials in the sub-10 nanometer size range. For example, with transistor gate lengths fast approaching sub-10 nm size range, highly conductive ultra-shallow junctions on the nanometer length scale are used to scale down transistor size to achieve faster transistor speeds and higher packing densities. Furthermore, a wide range of proposed miniaturized electronic applications incorporate nanowire building blocks or other non-planar conductive nanostructures that use doping.
Current methods are not suitable for doping to depths of less than 10 nm. Ion implantation involves the bombardment of silicon substrates with high-energy dopant ions that replace silicon atoms in the substrate lattice. However, the process also produces point defects and vacancies in the lattice, which interact with the dopants to broaden the junction profile, thereby limiting the formation of sub-10 nm doping profiles. Furthermore, ion implantation is incompatible with non-planar, nanostructured materials because the energetic ions have a significant probability of penetrating completely through the nanostructure without remaining in the lattice while causing significant crystal damage. On the other hand, conventional solid-source diffusion procedures lack control and uniformity when doping is to be conducted at depths of less than 10 nm.
Monolayer doping procedures overcome the difficulties of current technologies and achieve high-quality, sub-5 nm doping profiles with high areal uniformity. During this procedure, a highly uniform, covalently bonded monolayer of dopant-containing small molecules is formed on silicon surfaces. In a subsequent thermal annealing step, the dopant atoms are diffused into the silicon lattice. This approach has resulted in the demonstration of the shallowest junctions reported to date with low sheet resistivity for both p- and n-type doping, and is compatible with non-planar, restricted-dimension nanostructured substrates. However, the monolayer doping strategy uses a couple of steps that are cumbersome. Firstly, deposition of the dopant containing small molecules is carried out in an oxygen free atmosphere (i.e., in an inert atmosphere or in a vacuum) to prevent oxidative contamination. In addition, a silicon oxide capping layer is evaporated on top of the surface-functionalized silicon substrate before the annealing step in order to achieve efficient diffusion of the dopant atoms into the silicon substrate. The evaporation of the capping layer requires high vacuum of approximately ˜10−6 Torr.
Japanese Pat. App. JP 2005-123431 discloses forming an n-type diffusion zone by coating a film of an acidic organic phosphoric acid ester polymers (degree of polymerization of 500 or lower) dissolved in a polar organic solvent or water or a mixture thereof on a substrate followed by heating for a period of time at a first temperature that is lower than the diffusion temperature of phosphorus, then heating for a period of time in an oxidizing atmosphere at a second temperature that is higher than the first temperature but lower than the diffusion temperature of phosphorus, followed by heating for a period of time, such as 10 hours, in a non-oxidizing atmosphere at a third temperature that is higher than the second temperature in order to diffuse phosphorus into the substrate. This is a complex approach, necessitating three different heating cycles, and switching atmospheres between cycles. Also, the use of such polar solvents is often incompatible with standard processes used in semiconductor manufacture, possibly leading to poor film coating. If such a film is coated incompletely on the substrate, then the substrate will likely have a non-uniform doping of phosphorus.
Accordingly, it is desirable to develop a process for doping a substrate in ambient conditions without using a high vacuum and without using etching.